Static Ranges and Integer Expressions in Range Bounds - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

In VHDL, it was possible to declare an object by using the range of another object. For example:

for I in my_signal'range...

This would require that the range of my_signal be fixed, but if my_signal was declared as an unconstrained type, this would result in an error. VHDL-2008 now allows this by getting the range at the time of elaboration.