Initial Values - 2024.2 English - 2024.1 English

Initialize registers in Verilog-2001 when they are declared.

• The initial value:
  • Is a constant.
  • Cannot depend on earlier initial values.
  • Cannot be a function or task call.
  • Can be a parameter value propagated to the register.
  • Specifies all bits of a vector.
• When you assign a register as an initial value in a declaration, Vivado synthesis sets this value on the output of the register at global reset or power up.
• When a value is assigned in this manner:
  • The value is carried in the Verilog file as an INIT attribute on the register.
  • The value is independent of any local reset.