CASCADE_HEIGHT Verilog Example

CASCADE_HEIGHT Verilog Example - 2023.2 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2023-11-01

Version

2023.2 English

(* cascade_height = 16 *) reg [data_size-1:0] myram [2**addr_size-1:0];