Integer Handling in Concatenations - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2024.1 English

Unsigned integers in Verilog concatenations can cause unpredictable results. If you use an expression that results in an unsized integer, it does the following:

  • Assign the expression to a temporary signal.
  • Use the temporary signal in the concatenation.
reg [31:0] temp;
assign temp = 4'b1111 % 2;
assign dout = {12/3,temp,din};