Constrained and Unconstrained Ports - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

When defining a port, the port:

  • Can be constrained or unconstrained.
  • Are usually constrained.
  • Can be left unconstrained in the entity declaration.
    • If ports are left unconstrained, their width is defined at instantiation when the connection is made between formal ports and actual signals.
    • Unconstrained ports allow you to create different instantiations of the same entity, defining different port widths.

Array types of more than one-dimension are not accepted as ports. The entity declaration can also declare VHDL generics.