Interfaces - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

Interfaces provide a way to specify communication between blocks. An interface is a group of nets and variables that are grouped together to make connections between modules is easier to write. The syntax for a basic interface is:

interface interface_name; parameters and ports; items;
endinterface : interface_name

The interface_name at the end is optional but makes the code easier to read. For an example, see the following code:

module bottom1 ( input clk,
input [9:0] d1,d2, input s1,
input [9:0] result, output logic sel,
output logic [9:0] data1, data2, output logic equal);
//logic// endmodule
module bottom2 ( input clk, input sel,
input [9:0] data1, data2, output logic [9:0] result);
//logic// endmodule
module top ( input clk, input s1,
input [9:0] d1, d2, output equal);
logic [9:0] data1, data2, result; logic sel;
bottom1 u0 (clk, d1, d2, s1, result, sel, data1, data2, equal); bottom2 u1 (clk, sel, data1, data2, result);
endmodule

The previous code snippet instantiates two lower-level modules with some signals that are common to both.

These common signals can all be specified with an interface:

interface my_int 
logic sel;
logic [9:0] data1, data2, result; 
endinterface : my_int

In the two bottom-level modules, you can change to:

module bottom1 (
 my_int int1,
 input clk,
input [9:0] d1, d2,
 input s1,
output logic equal);

and

module bottom2 ( 
my_int int1, 
input clk);

Inside the modules, you can also change how you access sel, data1, data2, and result. According to the module, this is because there are no ports of these names. Instead, there is a port called my_int. This requires the following change:

if (sel)
result <= data1; 
to:
if (int1.sel)
int1.result <= int1.data1;

Finally, in the top-level module, the interface must be instantiated, and the instances reference the interface:

module top( 
input clk, 
input s1,
input [9:0] d1, d2, 
output equal);
my_int int3(); //instantiation
bottom1 u0 (int3, clk, d1, d2, s1, equal); 
bottom2 u1 (int3, clk);
endmodule