Generate Loop Statements - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

Use a generate-for loop to create one or more instances that can be placed inside a module.

Use the generate-for loop the same way you use a normal Verilog for loop, with the following limitations:

  • The generate-for loop index has a genvar variable.
  • The assignments in the for loop control refers to the genvar variable.
  • The contents of the for loop are enclosed by begin and end statements.
  • The begin statement is named with a unique qualifier.