Read each individual attribute for the rules on whether it should be placed on hierarchies or signals.
Generally, when an attribute is placed on a hierarchy, it affects only
that boundary and not the items inside that hierarchy. For example, placing a DONT_TOUCH on a specific level affects that level only, and
not the signals inside that level.
There are some exceptions to this rule. These are
DSP_FOLDING , RAM_STYLE,
ROM_STYLE, SHREG_EXTRACT, and
USE_DSP. When these attributes are placed on a hierarchy, they also
affect the signals inside that hierarchy.
Note: For the Verilog syntax of having the attribute inside
block comments, /* attr = value */, this attribute is attached to the next lexical item
after the comment. If the comment is on its own line, the next item in the RTL, no
matter how far down, gets the attribute. If the attribute is specified at the end of the
file, the attribute gets attached to the module.