Example with Custom Attribute on a Signal (Verilog) - 2024.2 English

Example with Custom Attribute on a Signal (Verilog) - 2024.2 English - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2024-11-13

Version

2024.2 English

(* my_att = "my_value", DONT_TOUCH = "yes" *) reg my_signal;