If-else- If and Case Generate - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

Previously in VHDL, if-generate statements took the form of the following:

if condition generate
--- statements
end generate;

An issue appears if you want to have different conditions; you would need to write multiple generates and be very careful with the ordering of the generates. VHDL-2008 supports if-else-if generate statements.

if condition generate
---statements
elsif condition2 generate
---statements
else generate
---statements
end generate;

In addition, VHDL-2008 also offers case-generate statements:

case expressions generate
when condition =>
statements
when condition2 =>
statements
end generate;