VHDL RESERVED Words - 2023.2 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
Release Date
2023.2 English
Table 1. VHDL RESERVED Words
abs access after alias
all and architecture array
assert attribute begin block
body buffer bus case
component configuration constant disconnect
downto else elsif end
entity exit file for
function generate generic group
guarded if impure in
inertial inout is label
library linkage literal loop
map mod nand new
next nor not null
of on open or
others out package port
postponed procedure process pure
range record register reject
rem report return rol
ror select severity signal
shared sla sll sra
srl subtype then to
transport type unaffected units
until use variable wait
when while with xnor