Verilog System Tasks and Functions - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

Vivado synthesis supports system tasks or function as shown in the following table. Vivado synthesis ignores unsupported system tasks.

Table 1. System Tasks and Status
System Task or Function Status Comment
$display Limited Support  
$fclose Not Supported  
$fdisplay Ignored  
$fgets Not Supported  
$finish Ignored  
$fopen Ignored  
$fscanf Ignored Escape sequences are limited to %b and %d
$fwrite Ignored  
$monitor Ignored  
$random Ignored  
$readmemb Supported  
$readmemh Supported  
$signed Supported  
$stop Ignored  
$strobe Ignored  
$time Ignored  
$unsigned Supported  
$write Not Supported  
$clog2 Supported This is supported with SystemVerilog only.
$floor Limited Support For parameters only.
$ceil Limited Support For parameters only.
$rtoi Supported  
$itor Supported  
$bits Supported  
$bitstoreal Supported  
$realtobits Supported  
$bitstoshortreal Supported  
$shortrealtobits Supported  
$unpacked_dimensions Supported  
$dimensions Supported  
$left Supported  
$right Supported  
$low Supported  
$high Supported  
$increment Supported  
$size Supported  
$countones Supported  
$countbits Supported  
$onehot Supported  
$onehot0 Supported  
$isunknown Supported  
$asin Supported  
$acos Supported  
$atan Supported  
$atan2 Supported  
$sinh Supported  
$cosh Supported  
$tanh Supported  
$sin Supported  
$asinh Supported  
$cos Supported  
$ascosh Supported  
$tan Supported  
$ln Supported  
$atanh Supported  
$log10 Supported  
$exp Supported  
$sqrt Supported  
$hypot Supported  
$pow Supported  
$fatal Supported  
$warning Supported  
$error Supported  
$info Supported  
all others Ignored