FULL_CASE (Verilog Only) - 2023.2 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
Release Date
2023.2 English

FULL_CASE indicates that all possible case values are specified in a case , casex , or casez statement. If case values are specified, extra logic for case values is not created by Vivado synthesis. This attribute is placed on the case statement.

Important: Because this attribute affects the compiler and can change the logical behavior of the design, it can be set in the RTL only.