ASYNC_REG - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

The ASYNC_REG is an attribute that affects many processes in the Vivado tools flow. The purpose of this attribute is to inform the tool that a register is capable of receiving asynchronous data in the D input pin relative to the source clock, or that the register is a synchronizing register within a synchronization chain. The Vivado synthesis, when encountering this attribute treats it as a DONT_TOUCH attribute and pushes the ASYNC_REG property forward in the netlist. This process ensures that the object with the ASYNC_REG property is not optimized out, and that tools later in the flow receive the property to handle it correctly.

For information on how other Vivado tools handle this attribute, see Vivado Design Suite Properties Reference Guide (UG912).

You can place this attribute on any register; values are FALSE (default) and TRUE . This attribute can be set in the RTL or the XDC.

Important: Care should be taken when putting this attribute on loadless signals. The attribute and signal might not be preserved. Attributes are case-insensitive, regardless of HDL.