Include Files - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

Verilog allows you to separate HDL source code into more than one file. To reference the code in another file, use the following syntax in the current file.

`include <path/file-to-be-included>

The previous line takes the contents of the file to be included and inserts it all into the current file at the line with the `include.

The path can be a relative or an absolute path. In the case of a relative path, the Verilog compiler looks in two different places for the file to be included.

  • The first is relative to the file with the `include statement. The compiler looks there, and if it can find the file, it inserts the contents of the file there.
  • The second place it looks is relative to the -include_dirs option in the Verilog options section of the General settings.

Multiple `include statements are allowed in the same Verilog file.