Previously in VHDL, both of the operands of the logical operators needed to be the same size.
VHDL-2008 supports using logical operators when one of the operands is an array
and one is a scalar. For example, to AND one bit with all the bits of a
vector, the following code was needed:
out1(3) <= in1(3) and in2;
out1(2) <= in1(2) and in2;
out1(1) <= in1(1) and in2;
out1(0) <= in1(0) and in2;
This can now be replaced with the following:
out1<= in1 and in2;