Verilog Parameter and Attribute Conflicts - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

Verilog parameter and attribute conflicts can arise because of the following:

  • Parameters and attributes can be applied to both instances and modules in the Verilog code.
  • Attributes can also be specified in a constraints file.