The Vivado IP catalog is designed, constrained, and validated with the Vivado Design Suite synthesis.
Note: Even though this is a synthesis setting,
-mode out_of_context does not trigger a full
resynthesis.Most AMD-delivered IP has HDL that is encrypted with IEEE P1735, and no support is available for third-party synthesis tools for AMD IP.
To instantiate AMD IP that is delivered with the Vivado IDE inside of a third-party synthesis tool, the following flow is recommended:
- Create the IP customization in a managed IP project.
- Generate the output products for the IP, including the synthesis design
checkpoint (DCP).
The Vivado IDE creates a stub HDL file, which is used in third-party synthesis tools to infer a black box for the IP (_stub.v | _stub.vhd). The stub file contains directives to prevent I/O buffers from being inferred; you might need to modify these files to support other synthesis tool directives.
- Synthesize the design with the stub files for the AMD IP.
- Use the netlist produced by the third-party synthesis tool and the DCP files for the AMD IP, run Vivado implementation. For more information, see Vivado Design Suite User Guide: Designing with IP (UG896).