RAM_DECOMP Verilog Example - 2024.2 English - 2024.1 English
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2024-11-13
Version
2024.2 English
(* ram_decomp = "power" *) reg [data_size-1:0] myram [2**addr_size-1:0];