Vivado synthesis supports the following Verilog-2001 features.
- Generate statements
- Combined port/data type declarations
- ANSI-style port list
- Module operator port lists
- ANSI C style task/function declarations
- Comma-separated sensitivity list
- Combinatorial logic sensitivity
- Default nets with continuous assigns
- Disable default net declarations
- Indexed vector part selects
- Multi-dimensional arrays
- Arrays of net and real data types
- Array bit and part selects
- Signed reg, net, and port declarations
- Signed-based integer numbers
- Signed arithmetic expressions
- Arithmetic shift operators
- Automatic width extension past 32 bits
- Power operator
- N-sized parameters
- Explicit in-line parameter passing
- Fixed local parameters
- Enhanced conditional compilation
- File and line compiler directives
- Variable part selects
- Recursive Tasks and Functions
- Constant Functions
For more information, see:
- Sutherland, Stuart. Verilog 2001: A Guide to the New Features of the Verilog Hardware Description Language (2002)
- IEEE Standard Verilog Hardware Description Language Manual (IEEE Standard1364-2001)