VHDL Concurrent Signal Assignments - VHDL Concurrent Signal Assignments - 2026.1 English - UG901

Concurrent signal assignments are concurrently active and re-evaluated when any signal on the right side of the assignment changes value. Assign the re-evaluated result to the left-hand-side signal.

Supported types of concurrent signal assignments are: Simple Signal Assignment Example, and Concurrent Selection Assignment Example (VHDL).