VHDL Assert Statements - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-06-28
Version
2024.1 English

Assert statements are supported with the -assert synthesis option.

CAUTION:
Care should be taken using asserts. Vivado can only support static asserts that do not create or are created by behavior. For example, performing as assert on a value of a constant or an operator/generic works; however, as an asset on the value of a signal inside an if statement does not work.