VHDL Entity Declarations - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

The I/O ports of the circuit are declared in the entity. Each port has a:

  • name
  • mode (in, out, inout, buffer)
  • type