Mixing VHDL and Verilog - 2024.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2024-05-30
Version
2024.1 English

The VHDL and Verilog files that make up a project are specified in a unique HDL project file. The rules for mixing VHDL and Verilog are, as follows:

  • Mixing VHDL and Verilog is restricted to design unit (cell) instantiation.
  • A Verilog module can be instantiated from VHDL code and a VHDL entity can be instantiated from Verilog code. No other mixing between VHDL and Verilog is supported. For example, you cannot embed Verilog source code directly in VHDL source code.
  • In a VHDL design, a restricted subset of VHDL types, generics, and ports is allowed on the boundary to a Verilog module. In a Verilog design, a restricted subset of Verilog types, parameters, and ports is allowed on the boundary to a VHDL entity or configuration. See VHDL and Verilog Boundary Rules.
  • Vivado synthesis binds VHDL design units to a Verilog module during HDL elaboration.