Verilog provides both behavioral and structural language structures. These structures allow the expression of design objects at high and low levels of abstraction.
- Designing hardware with Verilog allows the use of software concepts such
as:
- Parallel processing
- Object-oriented programming
- Verilog has a syntax similar to C and Pascal.
- Vivado synthesis supports Verilog as IEEE 1364.
- Verilog support in Vivado synthesis allows you to describe
the global circuit and each block in the most efficient style.
- Synthesis is performed with the best synthesis flow for each block.
- Synthesis in this context is the compilation of high-level behavioral and structural Verilog HDL statements into a flattened gate-level netlist. The netlist can be used to custom-program a programmable logic device such as a Virtex device.
- Different synthesis methods are used for:
- Arithmetic blocks
- Interconnect logic
- Finite State Machine (FSM) components
For information about basic Verilog concepts, see the IEEE Verilog HDL Reference Manual.