Using the TX Synchronous Gearbox

The TX synchronous gearbox requires the use of an external sequence counter that must be implemented in interconnect logic. The TX gearbox supports 2-byte, 4-byte, and 8-byte interfaces to the interconnect logic.

As shown in the following figure, the external sequence counter operating mode uses the CH*_TXSEQUENCE [6:0], CH*_TXDATA[127:0], and CH*_TXHEADER[5:0] inputs when in normal mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0). A binary counter must exist in the user logic to drive the CH*_TXSEQUENCE port. For 64B/66B encoding, the counter increments from 0 to 32 and repeats from 0. For 64B/67B encoding, the counter increments from 0 to 66 and repeats from 0. When using 64B/66B encoding, tie CH*_TXSQUENCE[6] to logic 0 and tie the unused CH*_TXHEADER bits to logic 0. The sequence counter increment ranges ({0 to 32}, {0 to 66}) are identical for 2-byte, 4-byte, and 8-byte interfaces. However, the counter must increment once every two TXUSRCLK2 cycles when using a mode where TX_DATA_WIDTH is the same as TX_INT_DATA_WIDTH (e.g., a 4-byte interconnect logic interface (TX_DATA_WIDTH = 32) and a 4-byte internal data width (TX_INT_DATA_WIDTH= 1)).

Figure 1. TX Synchronous Gearbox in External Sequence Counter Operating Mode in Normal Mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0)

Due to the nature of the 64B/66B and 64B/67B encoding schemes and the TX synchronous gearbox, user data is held (paused) during various sequence counter values. Data is paused for two TXUSRCLK2 cycles in modes with the same TX_DATA_WIDTH and TX_INT_DATA_WIDTH, and for one TXUSRCLK2 cycle in modes where TX_DATA_WIDTH is twice the TX_INT_DATA_WIDTH. Valid data transfer is resumed on the next TXUSRCLK2 cycle. The CH*_TXSEQUENCE pause locations for various modes are described in the following tables.

Table 1. 64B/66B Encoding Frequency of TXSEQUENCE and Pause Locations in Normal Mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = `1'b0`)
TX_DATA_WIDTH	TX_INT_DATAWIDTH	Frequency of TXSEQUENCE	TXSEQUENCE PAUSE
128 (16-byte)	2 (8-byte)	1 X TXUSRCLK2	32
64 (8-byte)	2 (8-byte)	2 X TXUSRCLK2	32
64 (8-byte)	1 (4-byte)	1 X TXUSRCLK2	32
32 (4-byte)	1 (4-byte)	2 X TXUSRCLK2	32
32 (4-byte)	0 (2-byte)	1 X TXUSRCLK2	31
16 (2-byte)	0 (2-byte)	2 X TXUSRCLK2	31

Table 2. 64B/67B Encoding Frequency of TXSEQUENCE and Pause Locations in Normal Mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = `1'b0`)
TX_DATA_WIDTH	TX_INT_DATAWIDTH	Frequency of TXSEQUENCE	TXSEQUENCE PAUSE
128 (16-byte)	2 (8-byte)	1 X TXUSRCLK2	22, 44, 66
64 (8-byte)	2 (8-byte)	2 X TXUSRCLK2	22, 44, 66
64 (8-byte)	1 (4-byte)	1 X TXUSRCLK2	22, 44, 66
32 (4-byte)	1 (4-byte)	2 X TXUSRCLK2	22, 44, 66
32 (4-byte)	0 (2-byte)	1 X TXUSRCLK2	21, 44, 65
16 (2-byte)	0 (2-byte)	2 X TXUSRCLK2	21, 44, 65

The following figure shows how a pause occurs at counter value 32 when using an 8-byte interconnect logic interface and a 4-byte internal datapath in external sequence counter mode with 64B/66B encoding in normal mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0).

Figure 2. Pause at Sequence Counter Value 32 in Normal Mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0)

The following figure shows how a pause occurs at counter value 44 when using a 2-byte interconnect logic interface with a 2-byte internal datapath in external sequence counter mode with 64B/67B encoding in normal mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0).

Figure 3. Pause at Sequence Counter Value 44 in Normal Mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0)

The sequence of transmitting 64/67 data for the external sequence counter mode using a 2-byte internal datapath (TX_INT_DATA_WIDTH = 0) in normal mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0) is:

Apply CH*_GTTXRESET and wait until the reset cycle is completed.
During reset, apply 7'h00 to CH*_TXSEQUENCE, header information to CH*_TXHEADER, and initial data to CH*_TXDATA. This state can be held indefinitely until data transmission is ready.
On count 0, apply data to CH*_TXDATA and header information to CH*_TXHEADER. For a 2‑byte interface (TX_DATA_WIDTH = 16), drive the second 2 bytes to CH*_TXDATA while still on count 0.
The sequence counter increments to 1 while data is driven on CH*_TXDATA.
After applying 4 bytes of data during count 1, the counter increments to 2. Apply data on CH*_TXDATA and header information on CH*_TXHEADER.
On count 21, stop data pipeline.
On count 22, drive data on CH*_TXDATA.
On count 44, stop data pipeline.
On count 45, drive data on CH*_TXDATA.
On count 65, stop data pipeline.
On count 66, drive data on CH*_TXDATA.

The sequence of transmitting 64/67 data for the external sequence counter mode using the 4-byte internal datapath (TX_INT_DATA_WIDTH = 1) in normal mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0) is as follows:

Apply CH*_GTTXRESET and wait until the reset cycle is completed.
During reset, apply 7'h00 to CH*_TXSEQUENCE, header information to CH*_TXHEADER, and initial data to CH*_TXDATA. This state can be held indefinitely until data transmission is ready.
On count 0, apply data to CH*_TXDATA and header information to CH*_TXHEADER. For a 4-byte interface (TX_DATA_WIDTH = 32), drive the second 4 bytes to CH*_TXDATA while still on count 0.
After applying 8 bytes of data, the counter increments to 1. Drive data on CH*_TXDATA and header information on CH*_TXHEADER.
On count 22, stop data pipeline.
On count 23, drive data on CH*_TXDATA.
On count 44, stop data pipeline.
On count 45, drive data on CH*_TXDATA.
On count 66, stop data pipeline.

The sequence of transmitting 64/67 data for the external sequence counter mode using an 8-byte internal datapath (TX_INT_DATA_WIDTH = 2) in normal mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0) is as follows:

Apply CH*_GTTXRESET and waits until the reset cycle is completed.
During reset, apply 6'h00 to CH*_TXSEQUENCE, the appropriate header data to CH*_TXHEADER, and initial data to CH*_TXDATA. This state can be held indefinitely until data transmission is ready.
On count 0, for an 8-byte interface (TX_DATA_WIDTH = 64), drive data onto CH*_TXDATA[63:0] and header information onto CH*_TXHEADER[2:0]. Continue to drive data and header information onto CH*_TXDATA[63:0] and CH*_TXHEADER[2:0] each TXUSRCLK cycle until count 22. For a 16-byte interface (TX_DATA_WIDTH = 128), apply data to both CH*_TXDATA[63:0], CH*_TXDATA[127:64], CH*_TXHEADER[2:0], and CH*_TXHEADER[5:3]. CH*_TXHEADER[2:0] is associated with CH*_TXDATA[63:0] while CH*_TXHEADER[5:3] is associated with TXDATA[127:64]. CH*_TXHEADER[5:3] and CH*_TXDATA[127:64] are serialized and transmitted first before TXHEADER[2:0] and CH*_TXDATA[63:0].
On count 22, stop data pipeline.
On count 23, resume driving data onto CH*_TXDATA and header information onto CH*_TXHEADER.
On count 44, stop data pipeline.
On count 45, resume driving data onto CH*_TXDATA and header information onto CH*_TXHEADER.
On count 66, stop data pipeline.

The sequence of transmitting 64/66 data for the external sequence counter mode using the 2-byte internal datapath (TX_INT_DATA_WIDTH = 0) in normal mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0) is as follows:

Apply CH*_GTTXRESET and wait until the reset cycle is completed.
During reset, apply 6'h00 to CH*_TXSEQUENCE, the appropriate header data to CH*_TXHEADER, and initial data to CH*_TXDATA. This state can be held indefinitely until data transmission is ready.
On count 0, apply data to CH*_TXDATA and header information to CH*_TXHEADER. For a 2‑byte interface (TX_DATA_WIDTH = 16), drive the second 2 bytes to CH*_TXDATA while still on count 0.
The sequence counter increments to 1 while data is driven on CH*_TXDATA.
After applying 4 bytes of data during count 1, the counter increments to 2. Drive data on CH*_TXDATA and header information on CH*_TXHEADER.
On count 31, stop data pipeline.
On count 32, drive data on CH*_TXDATA.

The sequence of transmitting 64/66 data for the external sequence counter mode using a 4-byte internal datapath (TX_INT_DATA_WIDTH = 1) in normal mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0) is as follows:

Apply CH*_GTTXRESET and waits until the reset cycle is completed.
During reset, apply 6'h00 to CH*_TXSEQUENCE, the appropriate header data to CH*_TXHEADER, and initial data to CH*_TXDATA. This state can be held indefinitely until data transmission is ready.
On count 0, drive data to CH*_TXDATA and header information to CH*_TXHEADER. For a 4-byte interface (TX_DATA_WIDTH = 32), drive the second 4 bytes to CH*_TXDATA while still on count 0.
After applying 8 bytes of data, the counter increments to 1. Drive data on CH*_TXDATA and header information on CH*_TXHEADER.
On count 32, stop data pipeline.

The sequence of transmitting 64/66 data for the external sequence counter mode using an 8-byte internal datapath (TX_INT_DATA_WIDTH = 2) in normal mode (CH*_TX_PCS_CFG0[2] (MODE[2]) = 1'b0) is as follows:

Apply CH*_GTTXRESET and waits until the reset cycle is completed.
During reset, apply 6'h00 to CH*_TXSEQUENCE, the appropriate header data to CH*_TXHEADER, and initial data to CH*_TXDATA. This state can be held indefinitely until data transmission is ready.
On count 0, for an 8-byte interface (TX_DATA_WIDTH = 64), drive data to CH*_TXDATA[63:0] and header information to CH*_TXHEADER[1:0]. Continue to drive data and header information on CH*_TXDATA[63:0] and CH*_TXHEADER[1:0] each TXUSRCLK cycle until count 32. For a 16-byte interface (TX_DATA_WIDTH = 128), apply data to CH*_TXDATA[63:0], CH*_TXDATA[127:64], CH*_TXHEADER[1:0], and CH*_TXHEADER[4:3]. CH*_TXHEADER[1:0] is associated with CH*_TXDATA[63:0] while CH*_TXHEADER[4:3] is associated with CH*_TXDATA[127:64]. CH*_TXHEADER[4:3] and CH*_TXDATA[127:64] are serialized and transmitted first before CH*_TXHEADER[1:0] and CH*_TXDATA[63:0].
On count 32, stop data pipeline.