Input Mode

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The reference clock input mode structure is illustrated in the following figure. The input is terminated internally with 50Ω on each leg to MGTAVCC. The reference clock is instantiated in software with the IBUFDS_GTE5 software primitive. The ports and attributes controlling the reference clock input are tied to the IBUFDS_GTE5 software primitive.

Figure 1. Reference Clock Input Structure
Important: Upon device configuration, the clock output from the IBUFDS_GTE5 which takes inputs from MGTREFCLK[0/1]P and MGTREFCLK[0/1]N can only be used under the following conditions:
  • The GTPOWERGOOD signal has already asserted High.