Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

This section shows how to configure and use each of the functional blocks inside the receiver (RX). Each transceiver includes an independent receiver made up of a PCS and a PMA. The following figure shows the blocks of the transceiver RX. High-speed serial data flows from traces on the board into the PMA of the transceiver RX, into the PCS, and finally into the interconnect logic. Refer to Ring PLL and LC-Tank PLL for the description of the channel clocking architecture, which provides clocks to the RX and TX clock dividers.

Figure 1. Transceiver RX Block Diagram

The key elements within the transceiver RX are:

  1. RX Analog Front End
  2. RX Out-of-Band Signaling
  3. RX Equalizer (DFE and LPM)
  4. RX CDR
  5. RX Fabric Clock Output Control
  6. RX Margin Analysis
  7. RX Polarity Control
  8. RX Pattern Checker
  9. RX Byte and Word Alignment
  10. RX 8B/10B Decoder
  11. RX Buffer Bypass
  12. RX Buffer
  13. RX Clock Correction
  14. RX Channel Bonding
  15. RX Synchronous Gearbox
  16. RX Interface