Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

Loopback modes are specialized configurations of the transceiver datapath where the traffic stream is folded back to the source. Typically, a specific traffic pattern is transmitted and then compared to check for errors. The following figure illustrates a loopback test configuration with four different loopback modes.

Figure 1. Loopback Testing Overview

Loopback test modes fall into two broad categories:

  • Near-end loopback modes loop transmit data back in the transceiver closest to the traffic generator. For Versal adaptive SoC GTY/GTYP transceivers, the serial data is still available on the TX differential output pairs.
  • Far-end loopback modes loop received data back in the transceiver at the far end of the link. For Versal adaptive SoC GTY/GTYP transceivers, the receive data is visible on the RXDATA interface as in normal operation.

Loopback testing can be used either during development or in deployed equipment for fault isolation. The traffic patterns used can be either application traffic patterns or specialized pseudo-random bit sequences. Each transceiver has a built-in PRBS generator and checker.

Each GTY transceiver features several loopback modes to facilitate testing:

  • Near-end PCS loopback (path 1 in Figure 1)

    The RX elastic buffer must be enabled for near-end PCS loopback to function properly. While in near-end PCS loopback, the RXPHYCLK domain is clocked by the TXPHYCLK parallel clock. If CH*_RXOUTCLK is used to clock interconnect logic, and RXOUTCLKSEL is set to RXPHYCLK during normal operation, one of these two settings must be made when placing the GTY transceiver into near-end PCS loopback:

    • Set RXOUTCLKCTL to select RXOUTPCSCLK, or
    • Set CH*_RXCDRHOLD = 1'b1
  • Near-end PMA loopback (path 2 in Figure 1)

  • Far-end PMA loopback (path 3 in Figure 1)

    The TX phase interpolator PPM controller must be disabled by setting the TXPIPPMEN and TXPIPPMSEL ports to 1'b0. A GTTXRESET is required after entering or exiting far-end PMA loopback. Additionally, TXPI_BYPASS (CH*_CHCLK_TXPI_CFG0[2]) should be set and cleared to enable far-end PMA loopback in asynchronous systems (REFCLKs have ppm difference).

  • Far-end PCS loopback (path 4 in Figure 1)

    If clock correction is not used, a transceiver in far-end PCS loopback must use the same reference clock used by the transceiver that is the source of the loopback data. Regardless of whether or not clock correction is used, the TXUSRCLK and RXUSRCLK ports must be driven by the same clocking resource (BUFG_GT). Far-end PCS loopback is not supported when both or either gearboxes in the channel are enabled.