RX Buffer Bypass in Single-Lane Auto Mode

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

Use these transceiver settings to bypass the RX buffer in single-lane mode:

  • CH*_RX_PHALIGN_CFG0[31] = 1'b1 (DLY_ALIGN_EN)
  • CH*_RX_PHALIGN_CFG0[30] = 1'b1 (PH_ALIGN_EN)
  • CH*_RX_PHALIGN_CFG0[17:16] = 2'b00 (SYNC_MODE)
  • CH*_RX_PHALIGN_CFG1[3:2] = 2'b00 (CHAIN_MODE)
  • CH*_PIPE_CTRL_CFG7[14:12] = 3'b010 or 3'b101 (RXOUTCLKCTL) to select either the recovered clock or the programmable divider clock as the source of RXOUTCLK

With the transceiver reference clock selected, RXOUTCLK is to be used as the source of RXUSRCLK. You must ensure that RXOUTCLK and the selected transceiver reference clocks are operating at the desired frequency. When the RX buffer is bypassed, the RX phase alignment procedure must be performed after these conditions:

  • Resetting or powering up the transceiver RX.
  • Resetting or powering up the RPLL and/or LCPLL.
  • Changing the RX recovered clock source or frequency.
  • Changing the TX line rate.

The following figure shows the required steps to perform the auto RX phase alignment and use the RX delay alignment to adjust RXUSRCLK to compensate for temperature and voltage variations.

Figure 1. RX Buffer Bypass—Single-Lane Auto Mode

  1. The sequence of events in this figure is not drawn to scale.
  2. After conditions such as a receiver reset or RX rate change, RX phase alignment must be performed to align PHYCLK and RXUSRCLK. The RX phase and delay alignments are initiated by asserting CH*_RXPHDLYRESET.
  3. RX phase alignment is done when the rising edge of CH*_RXSYNCDONE is detected. This signal should remain asserted until another alignment procedure is initiated.
  4. An assertion/deassertion of GTRXRESET is required if CH*_RXSYNCDONE does not follow the sequence shown in this figure.
  5. RX delay alignment continues to adjust RXUSRCLK to compensate for temperature and voltage variations.