Key Differences from Previous FPGA Generations

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
Release Date
1.3 English
  • Additional datapath to support CCIX
  • GTY/GTYP primitive is a single Quad instead of separate COMMON and CHANNEL primitives
  • Single USRCLK clocking scheme driven by TX/RXOUTCLK

The following figure illustrates the clustering of four transceiver channel (CHANNEL) blocks and two high speed clocking (HSCLK) blocks to form the GTYE5_QUAD primitive or GTYP_QUAD primitive.

Note: The GTY Quad primitive is called GTYE5_QUAD and GTYP Quad primitive is called GTYP_QUAD in Versal devices.
Figure 1. Transceiver Quad Configuration

Four CHANNEL blocks clustered together with two HSCLK blocks form a Quad or Q. Each HSCLK block contains one LC-tank PLL (LCPLL) and one ring oscillator PLL (RPLL). PLLs inside HSCLK0 can only provide a clock to CHANNEL0/1 and PLLs inside HSCLK1 can only provide a clock to CHANNEL2/3. Each CHANNEL block consists of a transmitter and a receiver. The following figure illustrates the topology of the GTY and GTYP channel.

Figure 2. Channel Topology

Refer to Ring PLL for the description of the channel clocking architecture, which provides clocks to the RX and TX clock dividers.