Interface Width Configuration

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The GTY and GTYP transceiver contains 2-byte, 4-byte, and 8-byte internal datapaths and is configurable by setting the RX_INT_DATA_WIDTH attribute. The interface width is configurable by setting the RX_DATA_WIDTH attribute. When the 8B/10B decoder is enabled, RX_DATA_WIDTH must be configured to 20 bits, 40 bits, or 80 bits, and in this case, the RX interface only uses the CH*_RXDATA ports. For example, CH*_RXDATA[15:0] is used when the interface width is 16. When the 8B/10B decoder is bypassed, RX_DATA_WIDTH can be configured to any of the available widths: 16, 20, 32, 40, 64, 80, 128, or 160 bits.

The following table shows how the interface width for the RX datapath is selected. 8B/10B decoding is described in more detail in RX 8B/10B Decoder.

Table 1. RX Interface Datapath Configuration
8B10B RX_DATA_WIDTH RX_INT_DATA_WIDTH Interface Width Internal Data Width
Disabled 4'b0010 2'b00 16 16
4'b0011 2'b00 20 20
4'b0100 2'b00 32 16
4'b0100 2'b01 32 32
4'b0101 2'b00 40 20
4'b0101 2'b01 40 40
4'b0110 2'b01 64 32
4'b0110 2'b10 64 64
4'b0111 2'b01 80 40
4'b0111 2'b10 80 80
4'b1000 2'b10 128 64
4'b1001 2'b10 160 80
Enabled 4'b0011 2'b00 16 20
4'b0101 2'b00 32 20
4'b0101 2'b01 32 40

When the 8B/10B decoder is bypassed and RX_DATA_WIDTH is 160, the CH*_RXCTRL0 and CH*_RXCTRL1 ports are used to extend the RXDATA port from 128 to 160 bits. The following figure shows the data received when the 8B/10B decoder is disabled. When the RX gearbox is used, refer to RX Synchronous Gearbox for data transmission order.

Figure 1. RX Data Received When 8B10B Decoder is Bypassed