Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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Each Quad contains two LC-based PLLs, one per HSCLK0/1 block, that are referred to as LCPLLs. Use of an LCPLL is required when operating the channels at line rates above the RPLL operating range. The GTYE5_QUAD/GTYP_QUAD primitives encapsulate both the LCPLLs and must be instantiated when either LCPLL is used.

The LCPLL input reference clock selection is described in Reference Clock Selection and Distribution. The LCPLL outputs feed the TX and RX clock divider blocks of the serial transceiver channels within the same Quad, which control the generation of serial and parallel clocks used by the PMA and PCS blocks. The LCPLL from HSCLK0 can only drive channel 0/1, and the LCPLL from HSCLK1 can only drive channel 2/3.

The following figure illustrates a conceptual view of the LCPLL architecture. The input clock can be divided by a factor of M before it is fed into the phase frequency detector. The feedback divider N determines the VCO multiplication ratio. For line rates 30.5 Gb/s and below, a fractional-N divider is supported where the effective ratio is a combination of the N factor plus a fractional part. The LCPLL output frequency depends on the setting of LCPLLCLKOUT_RATE. When LCPLLCLKOUT_RATE is set to HALF, the output frequency is half of the VCO frequency. When it is set to FULL, the output frequency is the same as the VCO frequency. A lock indicator block compares the frequencies of the reference clock and the VCO feedback clock to determine if a frequency lock has been achieved.

Figure 1. LCPLL Block Diagram

The LCPLL has a nominal operating range between 8.0 GHz to 16.375 GHz. For additional information regarding the exact LCPLL operating range for different device speed grades, refer to the Versal device data sheets. The Versal Adaptive SoC Transceivers Wizard chooses the appropriate LCPLL settings based on application requirements.

The following equation shows how to determine the LCPLL output frequency (GHz). For line rates above 30.5 Gb/s, the fractional part is bypassed.

Figure 2. LCPLL Output Frequency

The following equation shows how to determine the line rate (Gb/s). D represents the value of the TX or RX clock divider block in the channel.

Figure 3. Line Rate

The following equation shows how to determine the fractional part of the feedback divider presented in Figure 2.

Figure 4. Fractional Part

The following table lists the allowable divider values.

Table 1. LCPLL Divider Settings
Factor Attribute/Port Valid Settings
M LCPLL_PREDIV 1, 2, 3, 4



The valid divider range depends on whether or not the fractional component is enabled.

  1. Fractional component disabled: 13 – 160
  2. Fractional component enabled:
    1. 16 – 160 for line rates ≤ 25.78125 Gb/s
    2. 16 – 80 for line rates ≤ 30.5 Gb/s

The fractional component that is read or written in the register is N – 2. For N = 160, the value of N is 158.




1, 2, 4, 8, 16

[SDMWIDTH + 1:SDMWIDTH]: Two's complement integer in range [–2, 1]

[SDMWIDTH – 1:0]: fractional part in range [0, (2SDMWIDTH – 1)]