Transceiver Master Reset

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

A master reset controller is available in GTY and GTYP transceivers. The master reset controller automatically steps through the reset of the LCPLL, RPLL, ILO, TX programmable divider, RX programmable divider, TX channel, and RX channel. The master reset controller state machine operates as shown in Figure 1 for the TX and Figure 2 for the RX.

Figure 1. Transceiver TX Master Reset State Machine Sequence
Figure 2. Transceiver RX Master Reset State Machine Sequence

Each channel contains a master reset controller port for the given channel. In multi-lane protocols, the master reset signal should be toggled individually on all used lanes. However, ILORESETDONE and TX/RXRESETDONE signals can be daisy-chained to ensure that the previous step is completed on all lanes before the master reset controller proceeds. The TX/RXRESETDONE signals appear High after configuration, but more steps are required for the transceiver to be ready for use. TX/RXRESETDONE are Low during reset and before the PLLs lock. After reset is initiated, GTPOWERGOOD is High, and MSTTX/RXRESET is released, the TX/RXRESETDONE signals appear High, indicating that the transceiver is ready for use.