The transceiver resets can operate in two different modes: sequential mode and single mode.
- Sequential mode: The reset state machine starts with an initialization or component reset input driven High and proceeds through all states after the requested reset states in the reset state machine, as shown in Figure 1 for transceiver TX or Figure 1 for transceiver RX until completion. The completion of sequential mode reset flow is signaled when (TX/RX)RESETDONE transitions from Low to High.
- Single mode: The reset state machine only executes the requested component reset independently for a predetermined time set by its attribute. It does not process any state after the requested state, as shown in Figure 1 for transceiver TX or Figure 1 for transceiver RX. The requested reset can be any component reset to reset the PMA, the PCS, or functional blocks inside them.
The GTY and GTYP transceiver initialization reset must use sequential mode. All component resets can be operated in either sequential mode or single mode. The GTY and GTYP transceiver uses (TX/RX)RESETMODE to select between sequential reset mode and single reset mode. The following table provides configuration details that apply to both the transceiver TX and transceiver RX. Reset modes have no impact on LCPLL and RPLL resets. During normal operation, the transceiver TX or transceiver RX can be reset by applications in either sequential mode or single mode, which provides flexibility to reset a portion of the GTY and GTYP transceiver. When using either sequential mode or single mode, (TX/RX)RESETMODE must be set to the desired value 50 ns before the assertions of any reset.
Operation Mode | (TX/RX) RESETMODE |
---|---|
Sequential Mode |
2'b00
|
Single Mode |
2'b11
|
Port | Direction | Clock Domain | Description |
---|---|---|---|
CH[0/1/2/3]_RXRESETMODE[1:0] | In | Async | Reset mode port for RX.
|
CH[0/1/2/3]_TXRESETMODE[1:0] | In | Async | Reset mode port for TX.
|