Enabling Clock Correction

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

Each GTY and GTYP transceiver includes a clock correction circuit that performs clock correction by controlling the pointers of the dedicated 8B/10B elastic FIFO. The FIFO can only be enabled if the RX internal and external data width of the transceiver are the same. The supported modes are 2-byte/4-byte internal and external widths. To use clock correction, the dedicated 8B/10B elastic FIFO needs to be enabled and the general-purpose RX buffer disabled, along with the clock correction enable:

  • ELASTICBUF_8B10B_EN = 1'b1
  • EB8B10B_CLK_COR_USE = 1'b1

Prior to enabling the clock correction feature, the following settings should also be made (when clock correction is disabled):

  • EB8B10B_CLK_COR_SEQ_1_EN = 4'b1111
  • EB8B10B_CLK_COR_SEQ_2_EN = 4'b1111
  • EB8B10B_CLK_COR_SEQ_1_1 = 10'b0100000000
  • EB8B10B_CLK_COR_SEQ_2_1 = 10'b0100000000

Clock correction is only supported for internal data widths of 2 bytes (RX_INT_DATAWIDTH =0) and 4 bytes (RX_INT_DATAWIDTH = 1).