RX Gearbox Operating Modes

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The RX gearbox only supports 2-byte, 4-byte, and 8-byte logic interfaces to the interconnect logic.

As shown in the following figure, output ports CH*_RXDATA, CH*_RXHEADER, CH*_RXDATAOUTVALID, and CH*_RXHEADEROUTVALID, in addition to the CH*_RXGEARBOXSLIP input port are used in normal mode (MODE[2] = 1’b0).

Figure 1. Gearbox Usage in Normal Mode (MODE[2] = 1'b0)

The figure below shows an example of four cycles of data entering and exiting the RX gearbox for 64B/66B encoding when using a 4-byte logic interface (RX_DATA_WIDTH = 32 (4-byte), RX_INT_DATAWIDTH = 1 (4-byte)) in normal mode (MODE[2] = 1'b0).

Figure 2. RX Gearbox Operation in Normal Mode (MODE[2] = 1'b0)

Note: As per IEEE Std 802.3ae-2002 nomenclature, H1 corresponds to RxB<0>, H0 to RxB<1>, etc.

The RX gearbox internally manages all sequencing, which differs from the TX gearbox option of either internal or external sequencing. Depending on whether a 2-byte, 4-byte, or 8-byte interface is used, CH*_RXDATAOUTVALID and CH*_RXHEADEROUTVALID assert and deassert for different periods of length. The RX gearbox encounters similar data and header pauses found in the TX gearbox. RX Gearbox Operating Modes shows such a pause in addition to CH*_RXHEADERVALID and CH*_RXDATAVALID being deasserted for one cycle. RX Gearbox Operating Modes shows the operation for 64B/67B encoding when RX_DATA_WIDTH = 16 (2-byte) and RX_INT_DATAWIDTH = 0 (2-byte) in normal mode (MODE[2] = 1'b0).

Figure 3. RX Gearbox When Using 64B/66B Encoding and RX_DATA_WIDTH = 64 (8-Byte) and RX_INT_DATAWIDTH= 1 (4-Byte) in Normal Mode (MODE[2] = 1'b0)

Figure 4. RX Gearbox When Using 64B/67B Encoding and RX_DATA_WIDTH = 16 (2‑Byte) and RX_INT_DATAWIDTH = 0 (2‑Byte)