TX Buffer

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

In the transceiver TX datapath, the TX buffer acts as a buffer between two clock domains: the fabric (TXUSRCLK), and the PCS parallel clock (TXPHYCLK). To transmit data, the TXPHYCLK rate must match the TXUSRCLK rate, and all phase differences between the two domains must be resolved. The following figure shows the TXUSRCLK and TXPHYCLK domains. Additionally, the TX buffer supports 2:1 data width conversion.

Figure 1. TX Clock Domains

The transmitter includes a TX buffer and a TX phase alignment circuit to resolve phase differences between the TXPHYCLK and TXUSRCLK domains. The TX phase alignment circuit is used when the TX buffer is bypassed (see TX Buffer Bypass). All TX datapaths must use either the TX buffer or the TX phase-alignment circuit. The following table shows trade-offs between buffering and phase alignment.

Table 1. TX Buffering versus Phase Alignment
Parameter TX Buffer TX Phase Alignment
Ease of use The TX buffer is the recommended default to use when possible. It is robust and easier to operate. Phase alignment is an advanced feature that requires extra logic and additional constraints on clock sources. TXOUTCLKSEL must select the GTY/GTYP transceiver reference clock as the source of CH*_TXOUTCLK to drive TXUSRCLK.
Latency If low latency is critical, the TX buffer must be bypassed. Phase alignment uses fewer registers in the TX datapath to achieve lower and deterministic latency.
TX lane-to-lane deskew   The TX phase-alignment circuit can be used to reduce the lane skew between separate GTY/GTYP transceivers. All GTY/GTYP transceivers involved must use the same line rate.
TXUSRCLK jitter sensitivity No sensitivity to TXUSRCLK jitter. Sensitive to TXUSRCLK jitter.