TX Buffer Bypass in Multi-Lane Auto Mode with Asynchronous Gearbox (2:1 Mode)

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

In multi-lane with asynchronous gearbox mode, the TXUSRCLK domain is used to drive logic in the TXPHYCLK domain. When the TX fabric interface data width is twice the internal data width, the TX buffer is bypassed through the 2:1 REG. The 2:1 REG requires the phase alignment procedure to be performed identical to Figure 2. In this use case, note that the latency is still deterministic because the continuous phase alignment at 2:1 REG does not impact the data latency through the data path.

  • CH*_TX_PCS_CFG0[5] = 1'b1 (USE_BG)
  • CH*_TX_PHALIGN_CFG0[31] = 1'b1 (DLY_ALIGN_EN)
  • CH*_TX_PHALIGN_CFG0[30] = 1'b1 (PH_ALIGN_EN)
  • CH*_TX_PHALIGN_CFG0[17:16] = 2'b00 (SYNC_MODE) (All lanes are configured as slaves in multi-lane asynchronous gearbox mode)
  • CH*_TX_PHALIGN_CFG0[15] = 1'b1 (SYNC_MULTI_LANE)
  • CH*_TX_PHALIGN_CFG0[14] = 1'b1 (TXBUF_BYPASS_MODE)
  • CH*_TX_PHALIGN_CFG1[2:1] = 2'b00 (CHAIN_MODE)
  • CH*_TX_PHALIGN_CFG1[0] = 1'b1 (ASYNC_GBOX_PHALIGN_EN)
  • CH*_PIPE_CTRL_CFG7[2:0] = 3'b011 or 3'b101 (TXOUTCLKCTL) to select either the transceiver reference clock or the programmable divider clock as the source of TXOUTCLK