Parallel Clock Divider and Selector

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The parallel clock outputs from the RX clock divider control block can be used as an interconnect logic clock depending on the line rate and protocol requirements.

The recommended clock for the interconnect logic is the CH*_RXOUTCLK from one of the GTY or GTYP transceivers. It is also possible to bring the MGTREFCLK directly to the interconnect logic and use it as the interconnect logic clock. CH*_RXOUTCLK is preferred for general applications because it has an output delay control used for applications that bypass the RX buffer for constant datapath delay. Refer to RX Buffer Bypass for more details.

The RXOUTCLKCTL attribute controls the input selector and allows these clocks to be output via the CH*_RXOUTCLK port:

  • 3'b001: RXOUTPCSCLK path is not recommended to be used because it incurs extra delay from the PCS block.
  • 3'b010: RXPHYCLK is the recovered clock that can be brought out to the interconnect logic. The recovered clock is used by protocols that do not have a clock compensation mechanism and require to use a clock synchronous to the data (the recovered clock) to clock the downstream interconnect logic. It is also used by the RX PCS block. This clock is interrupted when the PLL or CDR is reset by one of the related reset signals.
  • 3'b011: RXREFCLKPMA is the input reference clock to the RPLL or LCPLL, depending on the RXOUTCLKCTL setting. For usages that do not require outputting a recovered clock to the interconnect logic, RXREFCLKPMA can be used as the system clock. However, CH*_TXOUTCLK is usually used as a system clock.
  • 3'b101: RXPROGDIVCLK is the divided down PLL clock after the RX programmable divider. See RX Fabric Clock Output Control for more details.
  • 3'b110: TXOUTCLK_PREDAPI is the clock source driving CH*_TXOUTCLK before going through the TX DAPI.