TX Receiver Detect Support for PCI Express Designs

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

The PCI Express specification includes a feature that allows the transmitter on a given link to detect if a receiver is present. The decision if a receiver is present is based on the rise time of TXP/TXN. TX Receiver Detect Support for PCI Express Designs shows the circuit model used for receive detection. The GTY/GTYP transceiver must be in the P1 power down state to perform receiver detection. Receiver detection requires an external coupling capacitor between the transmitter and receiver, and the receiver must be terminated. Refer to the PCI Express Base Specification for the actual value of the external coupling capacitor in Gen1, Gen2, Gen3, Gen4, or Gen5 (supported by GTYP only) applications. The receiver detection sequence starts with the assertion of CH*_TXDETECTRX. In response, the receiver detection logic drives TXN and TXP to (VDD - VSWING/2) and then releases them. The levels of TXN and TXP are compared with a threshold voltage. At the end of the sequence, the receiver detection status is presented on CH*_RXSTATUS when CH*_PHYSTATUS is asserted High for one cycle.

Figure 1. Receiver Detection Circuit Model

Note: Check the PCI Express Base Specification for the actual value of the external coupling capacitor in Gen1, Gen2, Gen3, Gen4, or Gen5 applications.