Transceiver RX component resets can be reset individually in either sequential mode or single mode. They are primarily used for special cases. These resets are needed when only a specific subsection needs to be reset.
Driving GTRXRESET from High to Low starts the component reset process. All RXPMARESETMASK and RXPCSRESETMASK bits along with RXRESETMODE must be held constant during the rest process.
When RXRESETMODE is set to sequential mode, the internal resets are toggled in sequence depending on the RXPMARESETMASK and RXPCSRESETMASK selection. When RXRESETMODE is set to single mode, the internal resets are toggled simultaneously depending on the RXPMARESETMASK and RXPCSRESETMASK selection.
In sequential mode, if the RX PCS is to be reset, RXUSERRDY must toggle High prior to the internal PCS reset signal being released, allowing RX reset to be completed.
Direct single reset ports EYESCANRESET, RXOOBRESET, RXCDRRESET, RXPRBSCNTRESET, and RXDPPCSRESET are available to perform single resets of the respective RX components. When direct single reset ports are toggled, a single reset is performed regardless of RXPMARESETMASK, RXPCSRESETMASK, and RXRESETMODE selection. These ports must be held Low during any sequential or single rests driven by GTRXRESET. In single mode, the RXRESETDONE port is not asserted.
The following table lists the recommended receiver resets for common situations.
Situation | Components to be Reset | Recommended RX Reset Setting | ||
---|---|---|---|---|
RXRESETMODE | RXPMARESETMASK | RXPCSRESETMASK | ||
After power up and configuration | RPLL, LCPLL, ILO, Entire RX |
2'b00
|
7'b1111111
|
5'b11111
|
After turning on a reference clock to the LCPLL/RPLL being used | RPLL, LCPLL, ILO, Entire RX |
2'b00
|
7'b1111111
|
5'b11111
|
After changing the reference clock to the LCPLL/RPLL being used | RPLL, LCPLL, ILO, Entire RX |
2'b00
|
7'b1111111
|
5'b11111
|
After assertion/deassertion of LCPLLPD or RPLLPD for the PLL being used | RPLL, LCPLL, ILO, Entire RX |
2'b00
|
7'b1111111
|
5'b11111
|
After assertion/deassertion of RXPD[1:0] | Entire RX |
2'b00
|
7'b1111111
|
5'b11111
|
RX rate change | RX PMA and RX PCS |
2'b00
|
7'b1111100
|
5'b11111
|
RX parallel clock source reset | RX PCS |
2'b00
|
7'b0000000
|
5'b11111
|
After remote power up | Entire RX |
2'b00
|
7'b1111111
|
5'b11111
|
Electrical Idle | Entire RX |
2'b00
|
7'b1111111
|
5'b11111
|
After connecting RXN/RXP | Entire RX |
2'b00
|
7'b1111111
|
5'b11111
|
After recovered clock becomes stable | RX Elastic Buffer |
2'b11
|
7'b0000000
|
5'b00100
|
After RX elastic buffer error | RX Elastic Buffer |
2'b11
|
7'b0000000
|
5'b00100
|
After changing channel bonding mode in real time | RX Elastic Buffer |
2'b11
|
7'b0000000
|
5'b00100
|
After PRBS error | PRBS Error Counter |
2'b11
|
7'b0000000
|
5'b00010
|
After comma alignment | RX Elastic Buffer |
2'b11
|
7'b0000000
|
5'b00100
|
Eye Scan reset only | Eye Scan |
2'b11
|
7'b0000000
|
5'b01000
|