The TX reset sequence shown in TX Initialization and Reset is not automatically started to follow global GSR. It must meet these conditions:
- TXRESETMODE must be set to sequential mode.
- GTTXRESET must be used.
- All TXPMARESETMASK, PCSRSVDIN[6:5] (TXDAPIRESETMASK), and TXPCSRESETMASK bits should be set to High.
- GTTXRESET cannot be driven Low until the associated PLL and ILO (if ILO is used in the TX) are locked.
- Ensure that GTPOWERGOOD is High before releasing LC/RPLLRESET, ILORESET (if ILO is used in the TX), and GTTXRESET.
If the reset mode is defaulted to single mode, then you must:
- Wait another 300–500 ns.
- Assert LCPLLRESET, ILORESET, RPLLRESET, and GTTXRESET following the reset sequence described in the following figure.
Alternatively, the master reset controller can be used to drive the PLL and TX reset in sequence automatically. Details can be found in Transceiver Master Reset.
Recommended: Use the
associated PLLLOCK from either LCPLL or RPLL to release GTTXRESET from High to Low
as shown in the figure. The TX reset state machine waits when GTTXRESET is detected
High and starts the reset sequence until GTTXRESET is released Low.
Figure 1. Transmitter Initialization after Configuration
