RX Buffer

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
Release Date
1.3 English

The transceiver RX datapath has two internal parallel clock domains used in the PCS: The PMA parallel clock domain (PHYCLK) and the RXUSRCLK domain. To receive data, the PMA parallel rate must be sufficiently close to the RXUSRCLK rate, and all phase differences between the two domains must be resolved. The following figure shows the two parallel clock domains: PHYCLK and RXUSRCLK.

Figure 1. RX Clock Domains

The GTY and GTYP transceivers include an RX buffer to resolve differences between the PHYCLK and RXUSRCLK domains. The RX buffer's location is highlighted in the previous figure. The phase of the two domains can also be matched by using the RX recovered clock from the transceiver to drive RXUSRCLK and adjusting its phase to match PHYCLK when the RX buffer is bypassed (see RX Buffer Bypass). The costs and benefits of each approach are shown in the following table.

Table 1. RX Buffering versus Phase Alignment
  RX Buffer RX Phase Alignment
Ease of Use The RX buffer is the recommended default to use when possible. It is robust and easier to operate. Phase alignment is an advanced feature that requires extra logic and additional constraints on clock sources. RXOUTCLKSEL must select the RX recovered clock as the source of CH*_RXOUTCLK to drive RXUSRCLK.
Clocking Options Can use RX recovered clock or local clock (with clock correction). Must use the RX recovered clock.
Initialization Must wait for all clocks to stabilize before buffer is reset. Must wait for all clocks to stabilize before performing the RX phase and delay alignment procedure.
Latency Buffer latency depends on feature use, such as clock correction and channel bonding. Phase alignment uses fewer registers in the RX datapath to achieve lower and deterministic latency.
RXUSRCLK Jitter Sensitivity No sensitivity to RXUSRCLK jitter. Sensitive to RXUSRCLK jitter.