The reference clock structure in the GTY/GTYP transceivers support two modes of operation: input mode and output mode. In the input mode of operation, your design provides a clock on the dedicated reference clock I/O pins that are used to drive the LCPLLs and RPLLs. In the output mode of operation, the recovered clocks (HSCLK*_RXRECCLKOUT0/1) from any of the four channels within the same Quad can be routed to the dedicated reference clock I/O pins. This output clock can then be used as the reference clock input at a different location. The mode of operation cannot be changed during runtime.