Reference Clock Selection and Distribution

The Versal adaptive SoC transceivers provide different reference clock input options. Clock selection supports two LCPLLs and two RPLLs.

From an architecture perspective, a Quad (or Q) contains four channels, two HSCLK blocks, two dedicated external reference clock pin pairs, and dedicated reference clock routing. The following list provides additional constraints on the above resources within a Quad.

• There is one RPLL and one LCPLL within each of the HSCLK0/1 blocks.
• PLLs from HSCLK0 can only provide clocking to Channel 0 and 1.
• PLLs from HSCLK1 can only provide clocking to Channel 2 and 3.

The GTYE5_QUAD or GTYP_QUAD primitives must be instantiated when any PLL or transceiver channel inside the Quad is used. In general, the reference clock for a Quad (Q(n)) can also be sourced from up to two Quads below (Q(n–1) or Q(n–2)) or from up to two Quads above (Q(n+1) or Q(n+2)). For devices that support stacked silicon interconnect (SSI) technology, the reference clock sharing is limited within its own super logic region (SLR).

See the Versal device data sheets for more information about SSI technology.

For Versal devices, sourcing of the reference clock is limited to two Quads above and below. Reference clock sharing is supported for all line rates.

Reference clock features include:

• Clock routing for northbound and southbound clocks.
• Flexible clock inputs available for the LCPLL or RPLL.
• Static or dynamic selection of the reference clock for the LCPLL or RPLL.

The Quad architecture has four GTY/GTYP transceivers, two dedicated reference clock pin pairs, and dedicated north or south reference clock routing. Each GTY/GTYP transceiver channel in a Quad has six clock inputs available according to the corresponding PLL resource assignments shown in the following table.

Because there are only two south clock inputs and four potential clock sources from the two Quads above (Q(n+1)) and Q(n+2)), only a maximum of two of the four potential reference clock pin pairs from above can be physically connected up to Q(n) at any given moment. The four potential reference clock pin pairs from above are reduced to two or three if the Quad above (Q(n+1)) is itself sourcing reference clock pin pairs from two above (Q(n+3)). This is because there are a total of two south reference clock routing tracks connecting the Quads. Similar rules apply when sourcing a reference clock from Quads below. Because there are two north clock inputs and four potential clock sources from the two Quads below (Q(n–1) and Q(n–2)), only a maximum of two of the four potential reference clock pin pairs from below can be physically connected up to Q(n) at any given moment. The four potential reference clock pin pairs from below is reduced to two or three if the Quad below (Q(n–1)) is itself sourcing reference clock pin pairs from two below Q(n–3). Again, this is because there are a total of two north reference clock routing tracks connecting the Quads. For example, Q(n–1) is sourcing both reference clocks from Q(n–3). In this example, Q(n) would only be able to source reference clock pins below from Q(n–1). Q(n) would not be able to access the reference clock pins in Q(n–2) because the two routing tracks have already been used to bring the two reference clocks from Q(n–3) to Q(n–1).

The following figure shows the detailed view of the reference clock multiplexer structure within a single HSCLK block, using LCPLL inside block HSCLK0 as an example. The same structure applies to LCPLL inside HSCLK1. When single or multiple reference clock sources are connected, the designer first needs to make sure that the connections are made to the correct PLLs using the reference clock ports assigned to the each intended PLL. The enhanced intelligent pin selection (IPS) automatically analyzes the design and maps reference clock selection during design implementation to guarantee that clocks are properly connected. For additional details on IPS, see Intelligent Pin Selection.

Similarly, the following figure shows the detailed view of the reference clock multiplexer structure within a single HSCLK block, but with RPLL being used inside HSCLK1 as another example. The connections for the two local GTREFCLKs are connected differently inside HSCLK1 compared to HSCLK0. HSCLK1_RPLL/LCPLLGTREFCLK1 is connected to input 1 on the input multiplexer while HSCLK1_RPLL/LCPLLGTREFCLK0 is connected to input 2 on the input multiplexer.

The following tables list the corresponding reference clock selection multiplexer settings.

As shown in Figure 1 and Figure 2, the GTY/ GTYP transceivers in Versal adaptive SoCs contain multiple dedicated reference clock input ports for each PLL. The user need to set the muxing of the reference clock input by using the selector port or the selector attribute. The following table lists the reference clock multiplexer selector control signals per PLL.