RX Buffer Bypass in Multi-Lane Auto Mode

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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For GTY and GTYP transceivers, when a multi-lane application requires RX buffer bypass, phase alignment is performed automatically. This section describes the steps required to perform the multi-lane RX buffer bypass alignment procedure automatically.

  • Initial Master: In a multi-lane application, the buffer bypass initial master is the lane that is the source of the RXOUTCLK.
    • CH*_RX_PHALIGN_CFG0[17:16] = 2'b01 (SYNC_MODE)
  • Maintenance Master: This lane shares the same RXUSRCLK that is generated from the RXOUCLK of the buffer bypass initial master. The maintenance master also provides delay skew information, which is forwarded internally to the initial master lane.
    • CH*_RX_PHALIGN_CFG0[17:16] = 2'b10 (SYNC_MODE)
  • Slave: These are all the lanes that share the same RXUSRCLK, which is generated from the RXOUCLK of the buffer bypass initial master.
    • CH*_RX_PHALIGN_CFG0[17:16] = 2'b00 (SYNC_MODE)

The following figure shows an example of buffer bypass initial master, maintenance master, and slave lanes.

Figure 1. RX Buffer Bypass Initial Master, Maintenance Master, and Slave Lanes

Use these transceiver settings to bypass the RX buffer in multi-lane mode:

  • CH*_RX_PHALIGN_CFG0[31] = 1'b1 (DLY_ALIGN_EN)
  • CH*_RX_PHALIGN_CFG0[30] = 1'b1 (PH_ALIGN_EN)
  • CH*_PIPE_CTRL_CFG7[14:12] = 3'b010 or 3'b101 (RXOUTCLKCTL) to select either the recovered clock or the programmable divider clock as the source of RXOUTCLK.

Multi-lane buffer bypass must only be used on lanes that have physical locations that are directly adjacent to one another. CH*_RX_PHALIGN_CFG1[3:2](CHAIN_MODE) must be set according to the physical location of the multi-lane group:

  • Top location: CH*_RX_PHALIGN_CFG1[3:2] = 2'b01 (CHAIN_MODE)
  • Middle location(s): CH*_RX_PHALIGN_CFG1[3:2] = 2'b11 (CHAIN_MODE)
  • Bottom location: CH*_RX_PHALIGN_CFG1[3:2] = 2'b10 (CHAIN_MODE)

The following timing diagram shows the required steps to perform auto RX phase and delay alignment.

Figure 2. RX Buffer Bypass - Multi-Lane Auto Mode

  1. The sequence of events shown in the figure is not drawn to scale.
  2. CH[IM]_* denotes ports related to the initial master lane.
  3. CH[MM]_* denotes ports related to the maintenance master lane.
  4. CH[S]_* denotes ports related to the slave lane(s).
  5. After conditions such as a transmitter reset or RX rate change, RX phase alignment must be performed to align PHYCLK and RXUSRCLK. The RX phase and delay alignments are initiated by asserting CH*_RXPHDLYRESET.
  6. RX phase alignment is done when the rising edge of CH[IM]_RXSYNCDONE is detected. This signal should remain asserted until another alignment procedure is initiated.
  7. An assertion/deassertion of GTRXRESET is required if CH[IM]_RXSYNCDONE does not follow the sequence shown in Figure 2.
  8. RX delay alignment continues to adjust RXUSRCLK to compensate for temperature and voltage variations.