RX Asynchronous Gearbox

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)
Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

The RX asynchronous gearbox only provides support for 64B/66B header and payload separation. The gearbox uses the output pins CH*_RXDATA[127:0] and CH*_RXHEADER[4:0] for the payload and header in normal (non-CAUI) mode. 64B/67B is not supported by the RX asynchronous gearbox.

The RX asynchronous gearbox supports a 4-byte, 8-byte, and 16-byte RX data interface to interconnect logic and requires the use of the 4-byte or 8-byte internal datapath. Scrambling of the data is done in the interconnect logic. The following table shows the valid data width combinations for the asynchronous gearbox.

Table 1. Valid Data Width Combinations for RX Asynchronous Gearbox
Internal Datapath Width Interface Width PHYCLK (MHz) RXUSRCLK (MHz)
32 1 32 TX Line Rate/32 TX Line Rate/33
32 2 64 TX Line Rate/32 TX Line Rate/66
64 1 64 TX Line Rate/64 TX Line Rate/66
64 2 128 TX Line Rate/64 TX Line Rate/132
  1. This configuration can be used for deterministic latency via measurement.
  2. This configuration requires the phase FIFO to be ON, and latency is not deterministic.

While the RX synchronous gearbox requires you to monitor the CH*_RXDATAVALID port because of invalid data appearing periodically, the RX asynchronous gearbox allows valid data to be continuously received every RXUSRCLK cycle. The following figure shows the location of the RX asynchronous gearbox. When a 4-byte internal datapath is selected (RX_INT_DATA_WIDTH = 1), 32 bits of data always enter the RX asynchronous gearbox on every RX PHYCLK cycle. Alternating 34 bits (2-bit header and 32-bit payload) and 32 bits (32-bit payload) of data exit the RX asynchronous gearbox every RXUSRCLK cycle. For an 8-byte internal datapath, 64 bits of data always enter the RX asynchronous gearbox on every RX PHYCLK cycle. 66 bits (2-bit header and 64-bit payload) of data exit the RX asynchronous gearbox every RXUSRCLK cycle.

Figure 1. RX Clock Domain Example (RX_INT_DATA_WIDTH = 1 (4-byte) and RX_DATA_WIDTH = 64)

When in normal mode, the datapath latency through the RX asynchronous gearbox is measured internally, and the reported latency can be accessed by reading a read-only register via the APB3. The RX asynchronous gearbox is used in conjunction with the RX programmable dividers. RXOUTCLKCTL must be set to 3'b101, and an appropriate divide value must be selected to create the required clock frequency for RXUSRCLK.