Using the RX Phase Buffer

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

For 8B/10B and 128B/130B datapaths, there are dedicated elastic FIFOs to resolve phase differences between the PHYCLK and RXUSRCLK domains. For other modes not doing RX clock correction or RX channel bonding and not using the RX buffer bypass, the dedicated RX buffer is used to resolve the phase differences between the PHYCLK and RXUSRCLK domains, and it is enabled by the following:


The content of the RX buffer becomes invalid if an RX buffer overflow or underflow condition occurs. When any of these conditions occur, reset and reinitialize the RX elastic buffer by using the GTRXRESET procedure or RX component reset procedure. The internally generated RX buffer reset can occur on channel bonding topology change, comma realignment, electrical idle, or rate change conditions.

The dedicated 8B/10B elastic FIFO is used for clock correction (see RX Clock Correction) and channel bonding (see RX Channel Bonding). The RX elastic buffer should be disabled in this use mode. For additional details, refer to the above two sections.