TX Fabric Clock Output Control

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The TX Clock Divider Control block has two main components: serial clock divider control and parallel clock divider and selector control. The clock divider and selector details are illustrated in the following figure.

Figure 1. TX Serial and Parallel Clock Divider
  1. CH*_TXOUTCLK is used as the source of the interconnect logic clock via BUFG_GT.

    The RPLL and LCPLL from HSCLK0 can only be used by TX channel 0/1, and RPLL and LCPLL from HSCLK1 can only be used by TX channel 2/3.

  2. The selection of the /2 and /4 divider block and /4, /5, /8, and /10 divider block is selected based on the TX_DATA_WIDTH and TX_INT_DATA_WIDTH.
  3. For details about placement constraints and restrictions on clocking resources (such as BUFG_GT and BUFG_GT_SYNC), refer to the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).
  4. The clock output from IBUFDS_GTE5 should only be used after GTPOWERGOOD asserts High.